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FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
Limp Home (LIMP)
The Limp Home mode of the component can be activated
by this digital input port. The signal is “high active”, meaning
the Fail mode can be activated by a logic high signal at the
input.
Ignition Input (IGN)
The Ignition input wakes the device. It also controls the
Fail Home mode activation. The signal is “high active”,
meaning the component is active in case of a logic high at the
input.
Flasher Input (FLASHER)
The Flasher input wakes the device. It also controls the
Fail mode activation. The signal is “high active”, meaning the
component is active in case of a logic high at the input.
Reset Input (RST)
This input wakes the device when the RST pin is at
logic [1]. It is also used to initialize the device configuration
and the SPI fault registers when the signal is low. All SI/SO
registers described in Table 9 and Table are reset. The fault
management is not affected by RST (see Figure 2 ).
Current Sense Output (CSNS)
The current sense output pin is an analog current output or
a voltage proportional to the temperature on the GND flag.
The routing to the common resistor is SPI programmable.
This current sense monitoring may be synchronized in
case of the OUT6 is not used. So, the current sense
monitoring can be synchronized with a rising edge on the
FETOUT pin (t CSNS(SYNC) ) if CSNS sync SPI bit is set to logic
[1]. Connection of the FETOUT pin to a MCU input pin allows
the MCU to sample the CSNS pin during a valid time-slot.
Since this falling edge is generated at the end of this timeslot,
upon a switch-off command, this feature may be used to
implement maximum current control.
Charge Pump (CP)
An external capacitor is connected between this pin and
FETOUT Output (FETOUT)
This output pin is used to control an external MOSFET
(OUT6).
The high level of the FETOUT Output is VCC if V BAT and
V CC are available in case of FETOUT is controlled ON.
FETOUT is not protected in case of a short-circuit or
under-voltage on V BAT .
In case of a reverse battery, OUT6 is OFF.
FETIN Input (FETIN)
This input pin gives the current recopy of the external
MOSFET. It can be routed on the CSNS output by a SPI
command.
SPI Protocol Description
The SPI interface has a full-duplex, three-wire
synchronous data transfer with four I /O lines associated with
it: Serial Clock (SCLK), Serial Input (SI), Serial Output (SO),
and Chip Select (CS).
The SI/SO pins of the 35XS3500 device follow a first-in,
first-out (D15 to D0) protocol, with both input and output
words transferring the most significant bit (MSB) first. All
inputs are compatible with 5.0 V CMOS logic levels supplied
by V CC .
The SPI lines perform the following functions:
Serial Clock (SCLK)
The SCLK pin clocks the internal shift registers of the
35XS3500 device. The SI pin accepts data into the input shift
register on the falling edge of the SCLK signal, while the SO
pin shifts data information out of the SO line driver on the
rising edge of the SCLK signal. It is important that the SCLK
pin be in a logic low state whenever CS makes any transition.
For this reason, it is recommended that the SCLK pin be in a
logic [0] whenever the device is not accessed (CS logic [1]
state). SCLK has a passive pull-down, R DWN . When CS is
logic [1], signals at the SCLK and SI pins are ignored and SO
is tri-stated (high-impedance) (see Figure 8 ).
the VBAT pin. It is used as a tank for the internal charge
pump. Its typical value is 100 nF ± 20%, 25 V maximum.
35XS3500
Analog Integrated Circuit Device Data ?
Freescale Semiconductor
21
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